Design Unit List

Here is a list of all design unit members with links to the Entities they belong to:

[detail level 12]

▼CChoose	\(Ch\) function block
CChoose.RTL	Architecture of the \(Ch\) function block
▼Ccounter	Upward counter
Ccounter.Behavioural	Architecture of the counter
▼CCS_adder	Carry-Save adder
CCS_adder.RTL	Architecture of the Carry Save Adder
▼CD_ff	Enabled D flip-flop with asynchronous reset
CD_ff.Behavioural	Architecture of the D flip-flop
▼CExpander_stage	Stage of the Expander pipeline
CExpander_stage.RTL	Architecture of the Expander pipeline stage
▼Cfull_adder	Full adder
Cfull_adder.RTL	Architecture of the full adder
▼Cfull_adder_array	Full adder array
Cfull_adder_array.RTL	Architectuere of the full adder array
▼CInitialisation_block	Initialisation block for the Compressor pipeline
CInitialisation_block.Reordered_UF2	Initialisation block for the Reordered_UF2 architecture of the transformation round block
▼CK_ROM	Constants ROM
CK_ROM.Behavioural	Architecture of the constants ROM
▼CLast_transformation	Last pipeline stage
CLast_transformation.RTL	Architecture of the last pipeline stage
▼CMajority	\(Maj\) function block
CMajority.RTL	Architecture of the \(Maj\) function block
▼CRC_adder	Ripple-Carry adder
CRC_adder.RTL	Architecture of the RC adder
▼Creg	D register
Creg.RTL	Architecture of the D register
▼CSHA2_Control_Unit	Control Unit for the hash core
CSHA2_Control_Unit.FSM	Finite State Machine to control the hash core
CSHA2_Control_Unit.Reordering	Finite State Machine with support for resource reordering
▼CSHA2_core	SHA-2 hash core
CSHA2_core.RTL	Architecture of the hash core
▼CSigma_0	\(\Sigma_0\) function block
CSigma_0.RTL	Architecture of the \(\Sigma_0\) function block
▼CSigma_1	\(\Sigma_1\) function block
CSigma_1.RTL	Architecture of the \(\Sigma_1\) function block
▼CT1	\(T_1\) step function block
CT1.RTL	Architecture of the \(T_1\) step function block
▼CT2	\(T_2\) step function block
CT2.RTL	Architecture of the \(T_2\) step function block
▼Ctest_SHA256_power_1A	Test bench 1A for the SHA-256 hash core
Ctest_SHA256_power_1A.Testbed	Detail of the test bench
▼Ctest_SHA256_power_1B	Test bench 1B for the SHA-256 hash core
Ctest_SHA256_power_1B.Testbed	Detail of the test bench
▼Ctest_SHA256_power_2A	Test bench 2A for the SHA-256 hash core
Ctest_SHA256_power_2A.Testbed	Detail of the test bench
▼Ctest_SHA256_power_5A	Test bench 5A for the SHA-256 hash core
Ctest_SHA256_power_5A.Testbed	Detail of the test bench
▼CTransf_round	Transformation round block for the Compressor pipeline
CTransf_round.Naive	Straightforward implementation of the transformation round
CTransf_round.Precomputed_UF1	Precomputed, non-unrolled architecture of the transformation round block
CTransf_round.Reordered_UF1	Spatially-reordered, non-unrolled architecture of the transformation round block
CTransf_round.Reordered_UF2	Spatially-reordered, 2-unrolled architecture of the transformation round block
▼CTransf_round_comb	Combinatorial part of the transformation round block
CTransf_round_comb.Naive	Straightforward architecture of the combinatorial part of the transformation round block
CTransf_round_comb.Unrolled	Unrolled architecture of the combinatorial part of the transformation round
▼CtSHA256_core	Single-message est bench for the SHA-256 hash core
CtSHA256_core.Testbench	Detail of the test bench
▼CtSHA256_core_multi	Multi-message test bench for the SHA-256 hash core
CtSHA256_core_multi.Testbench	Detail of the test bench
▼CtSHA512_core	Single-message test bench for the SHA-512 hash core
CtSHA512_core.Testbench	Detail of the test bench
▼Cw_sigma_0	\(\sigma_0\) function block
Cw_sigma_0.RTL	Architecture of the \(\sigma_0\) function block
▼Cw_sigma_1	\(\sigma_1\) function block
Cw_sigma_1.RTL	Architecture of the \(\sigma_1\) function block