Expander_stage Entity Reference

Stage of the Expander pipeline. More...

Inheritance diagram for Expander_stage:

Entities
RTL	architecture
	Architecture of the Expander pipeline stage. More...

Libraries
ieee
	Standard library.
components
	Basic integrated circuits components library.
shacomps
	Basic SHA components library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.
numeric_std
	Arithmetic library, included for the unsigned addition.

Generics
WORD_WIDTH	natural := 32
	Width of the words of the Expander.
UNROLLING_FACTOR	natural := 1
	Number of SHA-2 steps performed by a single round.

Ports
clk	in std_logic
	Clock of this component.
not_rst	in std_logic
	Active-low asynchronous reset signal.
en	in std_logic
	Enable signal.
end_major_cycle	in std_logic
	Derived pipeline clock.
W_in	in std_logic_vector ( 16 * WORD_WIDTH - 1 downto 0 )
	Input of the expander pipeline stage.
W	out std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )
	Expanded words for the current clock cycle.
W_out	out std_logic_vector ( 16 * WORD_WIDTH - 1 downto 0 )
	Output of the expander pipeline stage.

Detailed Description

Stage of the Expander pipeline.

Member Data Documentation

clk

clk in std_logic

Port

Clock of this component.

components

components

Library

Basic integrated circuits components library.

en

en in std_logic

Port

Enable signal.

end_major_cycle

end_major_cycle in std_logic

Port

Derived pipeline clock.

ieee

ieee

Library

Standard library.

not_rst

not_rst in std_logic

Port

Active-low asynchronous reset signal.

numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned addition.

shacomps

shacomps

Library

Basic SHA components library.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

UNROLLING_FACTOR

UNROLLING_FACTOR natural := 1

Generic

Number of SHA-2 steps performed by a single round.

W

W out std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )

Port

Expanded words for the current clock cycle.

W_in

W_in in std_logic_vector ( 16 * WORD_WIDTH - 1 downto 0 )

Port

Input of the expander pipeline stage.

W_out

W_out out std_logic_vector ( 16 * WORD_WIDTH - 1 downto 0 )

Port

Output of the expander pipeline stage.

WORD_WIDTH

WORD_WIDTH natural := 32

Generic

Width of the words of the Expander.