Precomputed_UF1 Architecture Reference

Precomputed, non-unrolled architecture of the transformation round block. More...

Libraries
ieee
	Standard library.
shacomps
	Basic SHA components library.
components
	Basic integrated circuits components library.

Use Clauses
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Signals
reg_input	std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )
	Output of the multiplexer, and input of the compressor pipeline register.
reg_output	std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )
	Output of the compressor pipeline register.
feedback	std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )
	Internal output signal, to be used as feedback input.
d_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the accumulator \(D\) input to the compressor round.
h_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the accumulator \(H\) input to the compressor round.
Maj_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Maj\) function block.
Ch_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Ch\) function block.
Sigma_0_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_0\) function block.
Sigma_1_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_1\) function block.
delta_reg_in	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\delta\) function.
delta_reg_out	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Precomputed value of the \(\delta\) function.
delta_first_reg_in	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Precomputed value of the \(\delta'\) function.
delta_first_reg_out	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Precomputed value of the \(\delta'\) function.
intermediate_sum2	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the addition of \(Ch\) and \(\Sigma_1\).
intermediate_sum3	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the Carry-Save Adder on the path for computing \(A\).

Instantiations
pipeline_reg	reg <Entity reg>
	Pipeline register of the compressor pipeline.
delta	CS_adder <Entity CS_adder>
	Adder for computing the \(\delta\) function.
delta_reg	reg <Entity reg>
	Precomputation register for the \(\delta\) value.
delta_first_reg	reg <Entity reg>
	Precomputation register for the \(\delta'\) value.
maj	Majority <Entity Majority>
	\(Maj\) function block
sigma0	Sigma_0 <Entity Sigma_0>
	\(\Sigma_0\) function block
ch	Choose <Entity Choose>
	\(Ch\) function block
sigma1	Sigma_1 <Entity Sigma_1>
	\(\Sigma_1\) function block
intermediate_csa	CS_adder <Entity CS_adder>
	Carry-Save Adder on the path for computing \(A\).

Aliases
d_in	is input ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )
	Input value of the accumulator \(D\).
h_in	is input ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(H\).
valid_reg	is reg_output ( 8 * WORD_WIDTH )
	Flag of validity for the register.
a_t	is reg_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )
	Value of the accumulator \(A\) input to the compressor round.
b_t	is reg_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )
	Value of the accumulator \(B\) input to the compressor round.
c_t	is reg_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )
	Value of the accumulator \(C\) input to the compressor round.
e_t	is reg_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )
	Value of the accumulator \(E\) input to the compressor round.
f_t	is reg_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )
	Value of the accumulator \(F\) input to the compressor round.
g_t	is reg_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )
	Value of the accumulator \(G\) input to the compressor round.
a_feedback	is feedback ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )
	Value of the accumulator \(A\) output from the compressor round.
b_feedback	is feedback ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )
	Value of the accumulator \(B\) output from the compressor round.
c_feedback	is feedback ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )
	Value of the accumulator \(C\) output from the compressor round.
d_feedback	is feedback ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )
	Value of the accumulator \(D\) output from the compressor round.
e_feedback	is feedback ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )
	Value of the accumulator \(E\) output from the compressor round.
f_feedback	is feedback ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )
	Value of the accumulator \(F\) output from the compressor round.
g_feedback	is feedback ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )
	Value of the accumulator \(G\) output from the compressor round.
h_feedback	is feedback ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the compressor round.
valid_out	is output ( 8 * WORD_WIDTH )
	Flag of validity for the output register.
a_out	is output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )
	Value of the accumulator \(A\) output from the stage.
b_out	is output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )
	Value of the accumulator \(B\) output from the stage.
c_out	is output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )
	Value of the accumulator \(C\) output from the stage.
d_out	is output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )
	Value of the accumulator \(D\) output from the stage.
e_out	is output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )
	Value of the accumulator \(E\) output from the stage.
f_out	is output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )
	Value of the accumulator \(F\) output from the stage.
g_out	is output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )
	Value of the accumulator \(G\) output from the stage.
h_out	is output ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the stage.

Detailed Description

Precomputed, non-unrolled architecture of the transformation round block.

Implementation of the architecture originally proposed in I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, and M. Morales-Sandoval, "FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256", Microprocess. Microsyst., vol. 37, no. 6-7, pp. 750-757, 2013.

Member Data Documentation

a_feedback

a_feedback is feedback ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the compressor round.

This temporary signal is employed to perform the feedback

a_out

a_out is output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the stage.

a_t

a_t is reg_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) input to the compressor round.

b_feedback

b_feedback is feedback ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the compressor round.

This temporary signal is employed to perform the feedback

b_out

b_out is output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the stage.

b_t

b_t is reg_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) input to the compressor round.

c_feedback

c_feedback is feedback ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the compressor round.

This temporary signal is employed to perform the feedback

c_out

c_out is output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the stage.

c_t

c_t is reg_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) input to the compressor round.

ch

ch Choose

Instantiation

\(Ch\) function block

Ch_o

Ch_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Ch\) function block.

components

components

Library

Basic integrated circuits components library.

d_feedback

d_feedback is feedback ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the compressor round.

This temporary signal is employed to perform the feedback

d_in

d_in is input ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Input value of the accumulator \(D\).

d_out

d_out is output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the stage.

d_t

d_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the accumulator \(D\) input to the compressor round.

This value is precomputed during the precomputation step, hence it is not read from the registers

delta

delta CS_adder

Instantiation

Adder for computing the \(\delta\) function.

delta_first_reg

delta_first_reg reg

Instantiation

Precomputation register for the \(\delta'\) value.

delta_first_reg_in

delta_first_reg_in std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Precomputed value of the \(\delta'\) function.

This signal is input to the precompuation register

delta_first_reg_out

delta_first_reg_out std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Precomputed value of the \(\delta'\) function.

This signal is output from the precompuation register

delta_reg

delta_reg reg

Instantiation

Precomputation register for the \(\delta\) value.

delta_reg_in

delta_reg_in std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\delta\) function.

This signal is input to the precompuation register

delta_reg_out

delta_reg_out std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Precomputed value of the \(\delta\) function.

This signal is output from the precompuation register

e_feedback

e_feedback is feedback ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the compressor round.

This temporary signal is employed to perform the feedback

e_out

e_out is output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the stage.

e_t

e_t is reg_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) input to the compressor round.

f_feedback

f_feedback is feedback ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the compressor round.

This temporary signal is employed to perform the feedback

f_out

f_out is output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the stage.

f_t

f_t is reg_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) input to the compressor round.

feedback

feedback std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Internal output signal, to be used as feedback input.

g_feedback

g_feedback is feedback ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the compressor round.

This temporary signal is employed to perform the feedback

g_out

g_out is output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the stage.

g_t

g_t is reg_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) input to the compressor round.

h_feedback

h_feedback is feedback ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the compressor round.

This temporary signal is employed to perform the feedback

h_in

h_in is input ( WORD_WIDTH - 1 downto 0 )

Alias

Input value of the accumulator \(H\).

h_out

h_out is output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the stage.

h_t

h_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the accumulator \(H\) input to the compressor round.

This value is precomputed during the precomputation step, hence it is not read from the registers

ieee

ieee

Library

Standard library.

intermediate_csa

intermediate_csa CS_adder

Instantiation

Carry-Save Adder on the path for computing \(A\).

intermediate_sum2

intermediate_sum2 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the addition of \(Ch\) and \(\Sigma_1\).

intermediate_sum3

intermediate_sum3 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the Carry-Save Adder on the path for computing \(A\).

maj

maj Majority

Instantiation

\(Maj\) function block

Maj_o

Maj_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Maj\) function block.

numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

pipeline_reg

pipeline_reg reg

Instantiation

Pipeline register of the compressor pipeline.

It works also as working register

reg_input

reg_input std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the multiplexer, and input of the compressor pipeline register.

reg_output

reg_output std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the compressor pipeline register.

shacomps

shacomps

Library

Basic SHA components library.

sigma0

sigma0 Sigma_0

Instantiation

\(\Sigma_0\) function block

sigma1

sigma1 Sigma_1

Instantiation

\(\Sigma_1\) function block

Sigma_0_o

Sigma_0_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_0\) function block.

Sigma_1_o

Sigma_1_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_1\) function block.

valid_out

valid_out is output ( 8 * WORD_WIDTH )

Alias

Flag of validity for the output register.

valid_reg

valid_reg is reg_output ( 8 * WORD_WIDTH )

Alias

Flag of validity for the register.