Testbed Architecture Reference

Detail of the test bench. More...

Processes
clock_process	( )
	Process for clock generation.
transient_process	( )
stim_process	( )
	Test process.

Constants
clock_period	time := 10 ns
	Clock period.
IV	std_logic_vector ( 255 downto 0 ) := x " 6a09e667 " & x " bb67ae85 " & x " 3c6ef372 " & x " a54ff53a " & x " 510e527f " & x " 9b05688c " & x " 1f83d9ab " & x " 5be0cd19 "
	Initialisation vector.

Signals
clk	std_logic := ' 0 '
	Clock signal.
not_rst	std_logic := ' 0 '
	Asynchronous active-low reset signal.
en	std_logic := ' 0 '
	Enable signal.
start	std_logic := ' 0 '
	Start signal.
ready	std_logic := ' 0 '
	When asserted, a new input can be provided.
completed	std_logic := ' 0 '
	When asserted, a new hash output is available.
M_blk	std_logic_vector ( 511 downto 0 ) := ( others = > ' 0 ' )
	Padded data block to test.
hash	std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
	Output hash value.

Instantiations
uut	SHA2_core <Entity SHA2_core>
	Unit Under Test.

Detailed Description

Detail of the test bench.

Member Function Documentation

clock_process()

clock_process

(

)

Process for clock generation.

stim_process()

stim_process ( )

Process

Test process.

transient_process()

transient_process ( )

Process

Member Data Documentation

clk

clk std_logic := ' 0 '

Signal

Clock signal.

clock_period

clock_period time := 10 ns

Constant

Clock period.

completed

completed std_logic := ' 0 '

Signal

When asserted, a new hash output is available.

en

en std_logic := ' 0 '

Signal

Enable signal.

hash

hash std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )

Signal

Output hash value.

IV

IV std_logic_vector ( 255 downto 0 ) := x " 6a09e667 " & x " bb67ae85 " & x " 3c6ef372 " & x " a54ff53a " & x " 510e527f " & x " 9b05688c " & x " 1f83d9ab " & x " 5be0cd19 "

Constant

Initialisation vector.

M_blk

M_blk std_logic_vector ( 511 downto 0 ) := ( others = > ' 0 ' )

Signal

Padded data block to test.

not_rst

not_rst std_logic := ' 0 '

Signal

Asynchronous active-low reset signal.

ready

ready std_logic := ' 0 '

Signal

When asserted, a new input can be provided.

start

start std_logic := ' 0 '

Signal

Start signal.

uut

uut SHA2_core

Instantiation

Unit Under Test.