Ripple-Carry adder.
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| RTL | architecture |
| | Architecture of the RC adder. More...
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| width | integer := 8 |
| | Width of the adder.
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| x | in std_logic_vector ( width - 1 downto 0 ) |
| | First input operand of the adder.
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| y | in std_logic_vector ( width - 1 downto 0 ) |
| | Second input operand of the adder.
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| c_in | in std_logic |
| | Carry input of the adder.
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| s | out std_logic_vector ( width - 1 downto 0 ) |
| | Sum output of the adder.
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| c_out | out std_logic |
| | Carry output of the adder.
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◆ c_in
Carry input of the adder.
◆ c_out
Carry output of the adder.
◆ ieee
| s out std_logic_vector ( width - 1 downto 0 ) |
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Port |
◆ std_logic_1164
Standard 9-values logic library.
◆ width
| x in std_logic_vector ( width - 1 downto 0 ) |
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Port |
First input operand of the adder.
| y in std_logic_vector ( width - 1 downto 0 ) |
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Port |
Second input operand of the adder.