Ripple-Carry adder.  
 More...
 | 
| RTL   | architecture | 
|   | Architecture of the RC adder.  More...
  | 
|   | 
 | 
 | width   | integer  :=   8   | 
|   | Width of the adder.  
  | 
 | 
 | x   |  in  std_logic_vector (    width -  1  downto   0  )  | 
|   | First input operand of the adder.  
  | 
| y   |  in  std_logic_vector (    width -  1  downto   0  )  | 
|   | Second input operand of the adder.  
  | 
| c_in   |  in  std_logic  | 
|   | Carry input of the adder.  
  | 
| s   |  out  std_logic_vector (    width -  1  downto   0  )  | 
|   | Sum output of the adder.  
  | 
| c_out   |  out  std_logic  | 
|   | Carry output of the adder.  
  | 
◆ c_in
Carry input of the adder. 
 
 
◆ c_out
Carry output of the adder. 
 
 
◆ ieee
  
  
      
        
          | s out  std_logic_vector (    width -  1  downto   0  )   | 
         
       
   | 
  
Port   | 
  
 
 
◆ std_logic_1164
Standard 9-values logic library. 
 
 
◆ width
  
  
      
        
          | x in  std_logic_vector (    width -  1  downto   0  )   | 
         
       
   | 
  
Port   | 
  
 
First input operand of the adder. 
 
 
  
  
      
        
          | y in  std_logic_vector (    width -  1  downto   0  )   | 
         
       
   | 
  
Port   | 
  
 
Second input operand of the adder.