SHA2_Control_Unit Entity Reference

Control Unit for the hash core. More...

Entities
FSM	architecture
	Finite State Machine to control the hash core. More...
Reordering	architecture
	Finite State Machine with support for resource reordering . More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.

Generics
CYCLES_PER_STAGE	natural := 1

Ports
clk	in std_logic
	Clock of this component.
not_rst	in std_logic
	Active-low asynchronous reset signal.
start	in std_logic
	When asserted, a new Padded Data Block to be hashed is present at input.
count_top	in std_logic
	Asserted when a round is over.
count_stages_top	in std_logic
	Asserted when the pipeline has been flushed.
not_reset_count	out std_logic
	Active-low signal to reset the step counter.
count	out std_logic
	Asserted during hash computation to enable step counting.
count_stages	out std_logic
	Asserted when no new Padded Data Block is available, in order to complete the ongoing hashes.
first_major_cycle	out std_logic
	Control signal to allow starting the hash core.
expander_init	out std_logic
	Control signal to initialises the expansion pipeline.
ready_cu	out std_logic
	Control signal asserted when the circuit can accept new inputs.

Detailed Description

Control Unit for the hash core.

It employs an external stage counter so as to be able to support a generic number of pipeline stages

Member Data Documentation

clk

clk in std_logic

Port

Clock of this component.

count

count out std_logic

Port

Asserted during hash computation to enable step counting.

count_stages

count_stages out std_logic

Port

Asserted when no new Padded Data Block is available, in order to complete the ongoing hashes.

count_stages_top

count_stages_top in std_logic

Port

Asserted when the pipeline has been flushed.

count_top

count_top in std_logic

Port

Asserted when a round is over.

CYCLES_PER_STAGE

CYCLES_PER_STAGE natural := 1

Generic

expander_init

expander_init out std_logic

Port

Control signal to initialises the expansion pipeline.

first_major_cycle

first_major_cycle out std_logic

Port

Control signal to allow starting the hash core.

This signal fixes end_major_cycle behaviour during the very first major cycle

ieee

ieee

Library

Standard library.

not_reset_count

not_reset_count out std_logic

Port

Active-low signal to reset the step counter.

not_rst

not_rst in std_logic

Port

Active-low asynchronous reset signal.

ready_cu

ready_cu out std_logic

Port

Control signal asserted when the circuit can accept new inputs.

This signal is used only in fully pipelined architectures. In other cases, it is always low

start

start in std_logic

Port

When asserted, a new Padded Data Block to be hashed is present at input.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.