full_adder_array Entity Reference

Full adder array. More...

Inheritance diagram for full_adder_array:

Entities
RTL	architecture
	Architectuere of the full adder array. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.

Generics
width	integer := 32

Ports
x	in std_logic_vector ( width - 1 downto 0 )
	First input operand of the full adder array.
y	in std_logic_vector ( width - 1 downto 0 )
	Second input operand of the full adder.
z	in std_logic_vector ( width - 1 downto 0 )
	Third input operand of the full adder.
s	out std_logic_vector ( width - 1 downto 0 )
	Sum output of the full adder array.
c	out std_logic_vector ( width - 1 downto 0 )
	Carry output vector of the full adder.

Detailed Description

Full adder array.

A bench of full adders. The carry output features one carry output bit per full adder, therefore is not aligned with the sum. Instead, each carry bit is aligned with the full adder which generates it. This particular alignment allows for the addition of the carry bit with the output sum, as performed in the Carry-Save adder

Member Data Documentation

c

c out std_logic_vector ( width - 1 downto 0 )

Port

Carry output vector of the full adder.

ieee

ieee

Library

Standard library.

s

s out std_logic_vector ( width - 1 downto 0 )

Port

Sum output of the full adder array.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

width

width integer := 32

Generic

x

x in std_logic_vector ( width - 1 downto 0 )

Port

First input operand of the full adder array.

y

y in std_logic_vector ( width - 1 downto 0 )

Port

Second input operand of the full adder.

z

z in std_logic_vector ( width - 1 downto 0 )

Port

Third input operand of the full adder.