- s -

• s : CS_adder , full_adder , full_adder_array , RC_adder
• shacomps : Expander_stage , Transf_round.Naive , Transf_round.Precomputed_UF1 , Transf_round.Reordered_UF1 , Transf_round.Reordered_UF2 , Transf_round_comb.Unrolled
• SHIFT_LENGTH : Expander_stage.RTL
• shift_register_in : Expander_stage.RTL
• SIGMA : Expander_stage.RTL
• sigma0 : Expander_stage.RTL
• sigma1 : Expander_stage.RTL
• sigma_0 : Transf_round.Reordered_UF1
• Sigma_0_o : T2.RTL , Transf_round.Precomputed_UF1
• sigma_0_t : Transf_round.Reordered_UF2
• sigma_0_t1 : Transf_round.Reordered_UF2
• sigma_1 : Transf_round.Reordered_UF1
• Sigma_1_o : T1.RTL , Transf_round.Precomputed_UF1
• sigma_1_t : Transf_round.Reordered_UF2
• sigma_1_t1 : Transf_round.Reordered_UF2
• STAGE : K_ROM
• stage : SHA2_core.RTL
• start : SHA2_Control_Unit , SHA2_core , test_SHA256_power_1A.Testbed , test_SHA256_power_1B.Testbed , test_SHA256_power_2A.Testbed , test_SHA256_power_5A.Testbed , tSHA256_core.Testbench , tSHA256_core_multi.Testbench , tSHA512_core.Testbench
• STATE_TYPE : SHA2_Control_Unit.FSM , SHA2_Control_Unit.Reordering
• std_logic_1164 : Choose , counter , CS_adder , D_ff , Expander_stage , full_adder , full_adder_array , Initialisation_block , K_ROM , Last_transformation , Majority , RC_adder , reg , SHA2_Control_Unit , SHA2_core , Sigma_0 , Sigma_1 , T1 , T2 , test_SHA256_power_1A , test_SHA256_power_1B , test_SHA256_power_2A , test_SHA256_power_5A , Transf_round , Transf_round_comb , tSHA256_core , tSHA256_core_multi , tSHA512_core , utils , w_sigma_0 , w_sigma_1