Finite State Machine with support for resource reordering . More...
Processes | |
| delay_process | ( clk , not_rst ) |
| Process implementing the feedback delay element. | |
| tau_process | ( current , start , count_top , count_stages_top ) |
| Process implementing the \(\tau\) function. | |
| omega_process | ( current ) |
| Process for the \(\omega\) function. | |
Types | |
| STATE_TYPE | ( reset , idle , first_load , second_load , compute , last_stages ) |
| Type used to represent the various states of the FSM. | |
Signals | |
| current | STATE_TYPE := reset |
| Current state of the FSM. | |
| prox | STATE_TYPE := reset |
| Next state of the FSM. | |
Detailed Description
Finite State Machine with support for resource reordering .
During the compute stage, the signal count enables the step counter so as to keep track of the computing progresses. This counter produces also the signal count_top, which is the pipeline clock signal end_major_cycle
During the last_stages stage, the stage counter is enabled by means of the the signal count_stages. The stage is exited when the pipeline has been fully flushed. However, it is not necessary to entirely flush the pipeline in order to start a new computation, since it is possible to reach the compute stage from these stages. Both the step counter and the stage counter are reset during the idle stage in order to start from a known value
The first_load stage is an unstable stage needed to load the pipeline, by keeping asserted the signal first_major_cycle. It is necessary because the first counting of the counter actually requires an additional clock cycle to assert the signal count_top, since this signal starts low, and is asserted when the counting value equals 0 during all but the very first computation. It is therefore necessary to estabilish the same number of cycles for every computation stage, even though this increases the circuit latency by one clock cycle. In fact, without this state the first stage would perform one step more than designed, leading to an incorrect result. To avoid the deassertion of the start primary input during this stage, which would lead to the clearing of the first pipeline register validity flag, the ready_cu signal is kept asserted during this state.
The second_load stage is an additional unstable stage required to align the values of the \(K\) constant with the other operands within the Compressor pipeline, again by keeping asserted the signal first_major_cycle. It is necessary because the ROM introduces a delay of one clock cycle between the update of its input and the presentation of the corresponding output, and this delay is not compensated within the data path when FIX_TIME is set to true. It is worth noting that this problem affects only the Compressor pipeline, and the expander_init signal must be deasserted in order to have the \(W\) operand aligned.
Member Function Documentation
◆ delay_process()
Process implementing the feedback delay element.
This process allows for state updating
◆ omega_process()
|
Process |
Process for the \(\omega\) function.
This process allows for outputs updating
Being this FSM a Moore machine, outputs depend only upon the current state
◆ tau_process()
|
Process |
Process implementing the \(\tau\) function.
This process implements the logic for state changing
Member Data Documentation
◆ current
|
Signal |
Current state of the FSM.
◆ prox
|
Signal |
Next state of the FSM.
◆ STATE_TYPE
|
Type |
Type used to represent the various states of the FSM.
