- p -

• p1_plus_p3_reg_in : Transf_round.Reordered_UF2
• p1_plus_p3_reg_out : Transf_round.Reordered_UF2
• p1_reg_in : Transf_round.Reordered_UF1
• p1_reg_out : Transf_round.Reordered_UF1
• p2_int : Transf_round.Reordered_UF2
• p2_reg_in : Transf_round.Reordered_UF1 , Transf_round.Reordered_UF2
• p2_reg_out : Transf_round.Reordered_UF1 , Transf_round.Reordered_UF2
• p3 : Transf_round.Reordered_UF2
• p4_feedback : Transf_round.Reordered_UF2
• p4_mux_out : Transf_round.Reordered_UF2
• p4_out : Transf_round.Reordered_UF2
• p4_star_feedback : Transf_round.Reordered_UF2
• p4_star_mux_out : Transf_round.Reordered_UF2
• p4_star_out : Transf_round.Reordered_UF2
• p4_star_reg_in : Transf_round.Reordered_UF2
• p4_star_reg_out : Transf_round.Reordered_UF2
• p5 : Transf_round.Reordered_UF2
• p6 : Transf_round.Reordered_UF2
• p_4 : Initialisation_block.Reordered_UF2
• p_4_star : Initialisation_block.Reordered_UF2
• PIPELINE_STAGES : SHA2_core
• PIPELINE_WORDS : SHA2_core
• PREFETCH_ROUNDS : SHA2_core
• PREFETCH_STEPS : Initialisation_block , K_ROM , SHA2_core.RTL
• prox : SHA2_Control_Unit.FSM , SHA2_Control_Unit.Reordering