Spatially-reordered, 2-unrolled architecture of the transformation round block. More...

Libraries
ieee
	Standard library.
shacomps
	Basic SHA components library.
components
	Basic integrated circuits components library.

Use Clauses
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Signals
feedback	*std_logic_vector ( 14 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Internal output signal, to be used as feedback input.
mux_output	*std_logic_vector ( 14 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Output of the multiplexer, and input of the precomputation stage.
reg_input	*std_logic_vector ( 11 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Input of the compressor pipeline register.
reg_output	*std_logic_vector ( 11 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Output of the compressor pipeline register.
p3	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Internal signal carrying the parameter \(p_3\).
p5	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Internal signal carrying the parameter \(p_5\).
p6	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Internal signal carrying the parameter \(p_6\).
sigma_0_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_0\) functional block for the step \(t\).
sigma_0_t1	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_0\) functional block for the step \(t+1\).
sigma_1_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_1\) functional block for the step \(t\).
sigma_1_t1	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_1\) functional block for the step \(t+1\).
maj_o_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Majority\) functional block for the step \(t\).
maj_o_t1	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Majority\) functional block for the step \(t+1\).
ch_o_t	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Choose\) functional block for the step \(t\).
p2_int	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Internal value of the parameter \(p_2\) to be used for other sums.
bigH_star_int	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Internal value of the parameter \(H^*\) to be used for other sums.
kw4_pre	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the sum \(K_{t+4}+W_{t+4}\) input to the prefetch register.
kw3_pre	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the sum \(K_{t+3}+W_{t+3}\) input to the prefetch register.
kw4	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the sum \(K_{t+4}+W_{t+4}\) for the stage.
kw3	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the sum \(K_{t+3}+W_{t+3}\) for the stage.

Instantiations
sigma0_t	Sigma_0 <Entity Sigma_0>
	\(\Sigma_0\) component for the computation of the step \(t\)
maj_t	Majority <Entity Majority>
	\(\Majority\) component for the computation of the step \(t\)
csa_1	CS_adder <Entity CS_adder>
	CSA 1.
sigma1_t	Sigma_1 <Entity Sigma_1>
	\(\Sigma_1\) component for the computation of the step \(t\)
ch_t	Choose <Entity Choose>
	\(\Choose\) component for the computation of the step \(t\)
csa_2	CS_adder <Entity CS_adder>
	CSA 2.
csa_3	CS_adder <Entity CS_adder>
	CSA 3.
ch_t1	Choose <Entity Choose>
	\(\Choose\) component for the computation of the step \(t+1\)
sigma1_t1	Sigma_1 <Entity Sigma_1>
	\(\Sigma_1\) component for the computation of the step \(t+1\)
csa_a	CS_adder <Entity CS_adder>
	CSA for computing the intermediate parameter \(A\).
csa_e	CS_adder <Entity CS_adder>
	CSA for computing the intermediate parameter \(e_{t+1}\).
pipeline_reg	reg <Entity reg>
	Pipeline register of the compressor pipeline.
kw3_reg	reg <Entity reg>
kw4_reg	reg <Entity reg>
sigma0_t1	Sigma_0 <Entity Sigma_0>
	\(\Sigma_0\) component for the computation of the step \(t+1\)
maj_t1	Majority <Entity Majority>
	\(\Majority\) component for the computation of the step \(t+1\)
csa_a_out	CS_adder <Entity CS_adder>
	CSA for computing the new value for the accumulator \(A\).

Aliases
x_mux_out	is mux_output** ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )**
	Value of the parameter \(X^*\) input for the stage.
bigh_mux_out	is mux_output** ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )**
	Value of the parameter \(H^*\) input for the stage.
p4_mux_out	is mux_output** ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )**
	Value of the parameter \(P_4\) input for the stage.
x_star_mux_out	is mux_output** ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )**
	Value of the parameter \(X^*\) input for the stage.
bigh_star_mux_out	is mux_output** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Value of the parameter \(H^*\) input for the stage.
p4_star_mux_out	is mux_output** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Value of the parameter \(P^*_4\) input for the stage.
a_mux_out	is mux_output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) input for the stage.
b_mux_out	is mux_output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) input for the stage.
c_mux_out	is mux_output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) input for the stage.
e_mux_out	is mux_output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) input for the stage.
f_mux_out	is mux_output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) input for the stage.
g_mux_out	is mux_output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) input for the stage.
bigH_star_reg_in	is reg_input** ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )**
	Precomputed value of the parameter \(H^*\) input to the pipeline register.
x_star_reg_in	is reg_input** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Precomputed value of the parameter \(X^*\) input to the pipeline register.
bigA_reg_in	is reg_input** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Precomputed value of the intermediate parameter \(A\) input to the pipeline register.
p4_star_reg_in	is reg_input** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Precomputed value of the parameter \(P^*_4\) input to the pipeline register.
p2_reg_in	is reg_input** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Precomputed value of the parameter \(p_2\) input to the pipeline register.
p1_plus_p3_reg_in	is reg_input** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Precomputed value of the parameter \(p_1_+p_3\) input to the pipeline register.
e_plus1_reg_in	is reg_input** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Precomputed next value of the accumulator \(E\) input to the pipeline register.
f_reg_in	is reg_input** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Precomputed value of the accumulator \(F\) input to the pipeline register.
e_reg_in	is reg_input** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Precomputed value of the accumulator \(E\) input to the pipeline register.
b_reg_in	is reg_input** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Precomputed value of the accumulator \(B\) input to the pipeline register.
a_reg_in	is reg_input ( WORD_WIDTH - 1 downto 0 )
	Precomputed value of the accumulator \(A\) input to the pipeline register.
valid_reg	is reg_output** ( 11 * WORD_WIDTH )**
	Flag of validity for the register.
bigH_star_reg_out	is reg_output** ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )**
	Value of the parameter \(H^*\) input to the final calculation phase.
x_star_reg_out	is reg_output** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Value of the parameter \(X^*\) input to the final calculation phase.
bigA_reg_out	is reg_output** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Value of the intermediate parameter \(A\) input to the final calculation phase.
p4_star_reg_out	is reg_output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the parameter \(p_2\) input to the final calculation phase.
p2_reg_out	is reg_output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the parameter \(p_2\) input to the final calculation phase.
p1_plus_p3_reg_out	is reg_output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the parameter \(p_1+p_3\) input to the final calculation phase.
e_plus1_reg_out	is reg_output** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Next value of the accumulator \(E\) input to the final calculation phase.
f_reg_out	is reg_output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(F\) input to the final calculation phase.
e_reg_out	is reg_output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(E\) input to the final calculation phase.
b_reg_out	is reg_output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(B\) input to the final calculation phase.
a_reg_out	is reg_output ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(A\) input to the final calculation phase.
x_feedback	is feedback** ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )**
	Value of the parameter \(X^*\) output from the compressor round.
bigh_feedback	is feedback** ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )**
	Value of the parameter \(h^*\) output from the compressor round.
p4_feedback	is feedback** ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )**
	Value of the parameter \(P_4\) output from the compressor round.
x_star_feedback	is feedback** ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )**
	Value of the parameter \(X^*\) output from the compressor round.
bigh_star_feedback	is feedback** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Value of the parameter \(H^*\) output from the compressor round.
p4_star_feedback	is feedback** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Value of the parameter \(P^*_4\) output from the compressor round.
a_feedback	is feedback** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) output from the compressor round.
b_feedback	is feedback** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) output from the compressor round.
c_feedback	is feedback** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) output from the compressor round.
d_feedback	is feedback** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the accumulator \(D\) output from the compressor round.
e_feedback	is feedback** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) output from the compressor round.
f_feedback	is feedback** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) output from the compressor round.
g_feedback	is feedback** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) output from the compressor round.
h_feedback	is feedback ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the compressor round.
valid_out	is output** ( 14 * WORD_WIDTH )**
	Flag of validity for the output register.
x_out	is output** ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )**
	Value of the parameter \(X^*\) output from the stage.
bigh_out	is output** ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )**
	Value of the parameter \(H^*\) output from the stage.
p4_out	is output** ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )**
	Value of the parameter \(P_4\) output from the stage.
x_star_out	is output** ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )**
	Value of the parameter \(X^*\) output from the stage.
bigh_star_out	is output** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Value of the parameter \(H^*\) output from the stage.
p4_star_out	is output** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Value of the parameter \(P^*_4\) output from the stage.
a_out	is output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) output from the stage.
b_out	is output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) output from the stage.
c_out	is output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) output from the stage.
d_out	is output** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the accumulator \(D\) output from the stage.
e_out	is output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) output from the stage.
f_out	is output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) output from the stage.
g_out	is output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) output from the stage.
h_out	is output ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the stage.
k4	*is K ( 2 WORD_WIDTH - 1 downto WORD_WIDTH )**
	Constant \(K\) for the step \(t+4\).
k3	is K ( WORD_WIDTH - 1 downto 0 )
	Constant \(K\) for the step \(t-3\).
w4	is W ( WORD_WIDTH - 1 downto 0 )
	Constant \(K\) for the step \(t+4\).
w3	*is W ( 2 WORD_WIDTH - 1 downto WORD_WIDTH )**
	Constant \(K\) for the step \(t-3\).

Detailed Description

Spatially-reordered, 2-unrolled architecture of the transformation round block.

Implementation of the architecture originally proposed in H. E. Michail, G. S. Athanasiou, V. Kelefouras, G. Theodoridis, and C. E. Goutis,"On the Exploitation of a High-Throughput SHA-256 FPGA Design for HMAC", ACM Trans. Reconfigurable Technol. Syst., vol. 5, no. 1, p. 2:1–2:28, 2012.

Member Data Documentation

◆ a_feedback

a_feedback is feedback ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ a_mux_out

a_mux_out is mux_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) input for the stage.

◆ a_out

a_out is output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the stage.

◆ a_reg_in

a_reg_in is reg_input ( WORD_WIDTH - 1 downto 0 )

Alias

Precomputed value of the accumulator \(A\) input to the pipeline register.

◆ a_reg_out

a_reg_out is reg_output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(A\) input to the final calculation phase.

◆ b_feedback

b_feedback is feedback ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ b_mux_out

b_mux_out is mux_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) input for the stage.

◆ b_out

b_out is output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the stage.

◆ b_reg_in

b_reg_in is reg_input ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Precomputed value of the accumulator \(B\) input to the pipeline register.

◆ b_reg_out

b_reg_out is reg_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(B\) input to the final calculation phase.

◆ bigA_reg_in

bigA_reg_in is reg_input ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Precomputed value of the intermediate parameter \(A\) input to the pipeline register.

◆ bigA_reg_out

bigA_reg_out is reg_output ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Value of the intermediate parameter \(A\) input to the final calculation phase.

◆ bigh_feedback

bigh_feedback is feedback ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )

Alias

Value of the parameter \(h^*\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ bigh_mux_out

bigh_mux_out is mux_output ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) input for the stage.

◆ bigh_out

bigh_out is output ( 13 * WORD_WIDTH - 1 downto 12 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) output from the stage.

◆ bigh_star_feedback

bigh_star_feedback is feedback ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ bigH_star_int

bigH_star_int std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Internal value of the parameter \(H^*\) to be used for other sums.

◆ bigh_star_mux_out

bigh_star_mux_out is mux_output ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) input for the stage.

◆ bigh_star_out

bigh_star_out is output ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) output from the stage.

◆ bigH_star_reg_in

bigH_star_reg_in is reg_input ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(H^*\) input to the pipeline register.

◆ bigH_star_reg_out

bigH_star_reg_out is reg_output ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )

Alias

Value of the parameter \(H^*\) input to the final calculation phase.

◆ c_feedback

c_feedback is feedback ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ c_mux_out

c_mux_out is mux_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) input for the stage.

◆ c_out

c_out is output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the stage.

◆ ch_o_t

ch_o_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Choose\) functional block for the step \(t\).

◆ ch_t

ch_t Choose

Instantiation

\(\Choose\) component for the computation of the step \(t\)

◆ ch_t1

ch_t1 Choose

Instantiation

\(\Choose\) component for the computation of the step \(t+1\)

◆ components

components

Library

Basic integrated circuits components library.

◆ csa_1

csa_1 CS_adder

Instantiation

CSA 1.

◆ csa_2

csa_2 CS_adder

Instantiation

CSA 2.

◆ csa_3

csa_3 CS_adder

Instantiation

CSA 3.

◆ csa_a

csa_a CS_adder

Instantiation

CSA for computing the intermediate parameter \(A\).

◆ csa_a_out

csa_a_out CS_adder

Instantiation

CSA for computing the new value for the accumulator \(A\).

◆ csa_e

csa_e CS_adder

Instantiation

CSA for computing the intermediate parameter \(e_{t+1}\).

◆ d_feedback

d_feedback is feedback ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ d_out

d_out is output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the stage.

◆ e_feedback

e_feedback is feedback ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ e_mux_out

e_mux_out is mux_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) input for the stage.

◆ e_out

e_out is output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the stage.

◆ e_plus1_reg_in

e_plus1_reg_in is reg_input ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Precomputed next value of the accumulator \(E\) input to the pipeline register.

◆ e_plus1_reg_out

e_plus1_reg_out is reg_output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Next value of the accumulator \(E\) input to the final calculation phase.

◆ e_reg_in

e_reg_in is reg_input ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(E\) input to the pipeline register.

◆ e_reg_out

e_reg_out is reg_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) input to the final calculation phase.

◆ f_feedback

f_feedback is feedback ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ f_mux_out

f_mux_out is mux_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) input for the stage.

◆ f_out

f_out is output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the stage.

◆ f_reg_in

f_reg_in is reg_input ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(F\) input to the pipeline register.

◆ f_reg_out

f_reg_out is reg_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) input to the final calculation phase.

◆ feedback

feedback std_logic_vector ( 14 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Internal output signal, to be used as feedback input.

◆ g_feedback

g_feedback is feedback ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ g_mux_out

g_mux_out is mux_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) input for the stage.

◆ g_out

g_out is output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the stage.

◆ h_feedback

h_feedback is feedback ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ h_out

h_out is output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the stage.

◆ ieee

ieee

Library

Standard library.

◆ k3

k3 is K ( WORD_WIDTH - 1 downto 0 )

Alias

Constant \(K\) for the step \(t-3\).

◆ k4

k4 is K ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Constant \(K\) for the step \(t+4\).

◆ kw3

kw3 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the sum \(K_{t+3}+W_{t+3}\) for the stage.

◆ kw3_pre

kw3_pre std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the sum \(K_{t+3}+W_{t+3}\) input to the prefetch register.

◆ kw3_reg

kw3_reg reg

Instantiation

◆ kw4

kw4 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the sum \(K_{t+4}+W_{t+4}\) for the stage.

◆ kw4_pre

kw4_pre std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the sum \(K_{t+4}+W_{t+4}\) input to the prefetch register.

◆ kw4_reg

kw4_reg reg

Instantiation

◆ maj_o_t

maj_o_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Majority\) functional block for the step \(t\).

◆ maj_o_t1

maj_o_t1 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Majority\) functional block for the step \(t+1\).

◆ maj_t

maj_t Majority

Instantiation

\(\Majority\) component for the computation of the step \(t\)

◆ maj_t1

maj_t1 Majority

Instantiation

\(\Majority\) component for the computation of the step \(t+1\)

◆ mux_output

mux_output std_logic_vector ( 14 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the multiplexer, and input of the precomputation stage.

◆ numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

◆ p1_plus_p3_reg_in

p1_plus_p3_reg_in is reg_input ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(p_1_+p_3\) input to the pipeline register.

◆ p1_plus_p3_reg_out

p1_plus_p3_reg_out is reg_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the parameter \(p_1+p_3\) input to the final calculation phase.

◆ p2_int

p2_int std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Internal value of the parameter \(p_2\) to be used for other sums.

◆ p2_reg_in

p2_reg_in is reg_input ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(p_2\) input to the pipeline register.

◆ p2_reg_out

p2_reg_out is reg_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the parameter \(p_2\) input to the final calculation phase.

◆ p3

p3 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Internal signal carrying the parameter \(p_3\).

◆ p4_feedback

p4_feedback is feedback ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )

Alias

Value of the parameter \(P_4\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ p4_mux_out

p4_mux_out is mux_output ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )

Alias

Value of the parameter \(P_4\) input for the stage.

◆ p4_out

p4_out is output ( 12 * WORD_WIDTH - 1 downto 11 * WORD_WIDTH )

Alias

Value of the parameter \(P_4\) output from the stage.

◆ p4_star_feedback

p4_star_feedback is feedback ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Value of the parameter \(P^*_4\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ p4_star_mux_out

p4_star_mux_out is mux_output ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Value of the parameter \(P^*_4\) input for the stage.

◆ p4_star_out

p4_star_out is output ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Value of the parameter \(P^*_4\) output from the stage.

◆ p4_star_reg_in

p4_star_reg_in is reg_input ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(P^*_4\) input to the pipeline register.

◆ p4_star_reg_out

p4_star_reg_out is reg_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the parameter \(p_2\) input to the final calculation phase.

◆ p5

p5 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Internal signal carrying the parameter \(p_5\).

◆ p6

p6 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Internal signal carrying the parameter \(p_6\).

◆ pipeline_reg

pipeline_reg reg

Instantiation

Pipeline register of the compressor pipeline.

It works also as working register

◆ reg_input

reg_input std_logic_vector ( 11 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Input of the compressor pipeline register.

◆ reg_output

reg_output std_logic_vector ( 11 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the compressor pipeline register.

◆ shacomps

shacomps

Library

Basic SHA components library.

◆ sigma0_t

sigma0_t Sigma_0

Instantiation

\(\Sigma_0\) component for the computation of the step \(t\)

◆ sigma0_t1

sigma0_t1 Sigma_0

Instantiation

\(\Sigma_0\) component for the computation of the step \(t+1\)

◆ sigma1_t

sigma1_t Sigma_1

Instantiation

\(\Sigma_1\) component for the computation of the step \(t\)

◆ sigma1_t1

sigma1_t1 Sigma_1

Instantiation

\(\Sigma_1\) component for the computation of the step \(t+1\)

◆ sigma_0_t

sigma_0_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_0\) functional block for the step \(t\).

◆ sigma_0_t1

sigma_0_t1 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_0\) functional block for the step \(t+1\).

◆ sigma_1_t

sigma_1_t std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_1\) functional block for the step \(t\).

◆ sigma_1_t1

sigma_1_t1 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_1\) functional block for the step \(t+1\).

◆ valid_out

valid_out is output ( 14 * WORD_WIDTH )

Alias

Flag of validity for the output register.

◆ valid_reg

valid_reg is reg_output ( 11 * WORD_WIDTH )

Alias

Flag of validity for the register.

◆ w3

w3 is W ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Constant \(K\) for the step \(t-3\).

◆ w4

w4 is W ( WORD_WIDTH - 1 downto 0 )

Alias

Constant \(K\) for the step \(t+4\).

◆ x_feedback

x_feedback is feedback ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ x_mux_out

x_mux_out is mux_output ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) input for the stage.

◆ x_out

x_out is output ( 14 * WORD_WIDTH - 1 downto 13 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) output from the stage.

◆ x_star_feedback

x_star_feedback is feedback ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ x_star_mux_out

x_star_mux_out is mux_output ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) input for the stage.

◆ x_star_out

x_star_out is output ( 11 * WORD_WIDTH - 1 downto 10 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) output from the stage.

◆ x_star_reg_in

x_star_reg_in is reg_input ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(X^*\) input to the pipeline register.

◆ x_star_reg_out

x_star_reg_out is reg_output ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Value of the parameter \(X^*\) input to the final calculation phase.

Libraries

Use Clauses

Signals

Instantiations

Aliases

Detailed Description

Member Data Documentation

◆ a_feedback

◆ a_mux_out

◆ a_out

◆ a_reg_in

◆ a_reg_out

◆ b_feedback

◆ b_mux_out

◆ b_out

◆ b_reg_in

◆ b_reg_out

◆ bigA_reg_in

◆ bigA_reg_out

◆ bigh_feedback

◆ bigh_mux_out

◆ bigh_out

◆ bigh_star_feedback

◆ bigH_star_int

◆ bigh_star_mux_out

◆ bigh_star_out

◆ bigH_star_reg_in

◆ bigH_star_reg_out

◆ c_feedback

◆ c_mux_out

◆ c_out

◆ ch_o_t

◆ ch_t

◆ ch_t1

◆ components

◆ csa_1

◆ csa_2

◆ csa_3

◆ csa_a

◆ csa_a_out

◆ csa_e

◆ d_feedback

◆ d_out

◆ e_feedback

◆ e_mux_out

◆ e_out

◆ e_plus1_reg_in

◆ e_plus1_reg_out

◆ e_reg_in

◆ e_reg_out

◆ f_feedback

◆ f_mux_out

◆ f_out

◆ f_reg_in

◆ f_reg_out

◆ feedback

◆ g_feedback

◆ g_mux_out

◆ g_out

◆ h_feedback

◆ h_out

◆ ieee

◆ k3

◆ k4

◆ kw3

◆ kw3_pre

◆ kw3_reg

◆ kw4

◆ kw4_pre

◆ kw4_reg

◆ maj_o_t

◆ maj_o_t1

◆ maj_t

◆ maj_t1

◆ mux_output

◆ numeric_std

◆ p1_plus_p3_reg_in

◆ p1_plus_p3_reg_out

◆ p2_int

◆ p2_reg_in