Last_transformation Entity Reference

Last pipeline stage. More...

Entities
RTL	architecture
	Architecture of the last pipeline stage. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Generics
WORD_WIDTH	natural := 32
	Word width of the circuit.

Ports
h_in	in std_logic_vector ( 8 * WORD_WIDTH downto 0 )
	Newly computed values of the accumulators.
iv	in std_logic_vector ( 8 * WORD_WIDTH - 1 downto 0 )
	Old values of the accumulators.
h_out	out std_logic_vector ( 8 * WORD_WIDTH downto 0 )
	New intermediate hash value.

Detailed Description

Last pipeline stage.

Combinatorial component which performs the final sum between the old values of the accumulators and the newly computed values to get the new intermediate hash value

The MSB of the input, which is the validity flag of the pipeline registers, is simply propagated to the output

Member Data Documentation

h_in

h_in in std_logic_vector ( 8 * WORD_WIDTH downto 0 )

Port

Newly computed values of the accumulators.

h_out

h_out out std_logic_vector ( 8 * WORD_WIDTH downto 0 )

Port

New intermediate hash value.

ieee

ieee

Library

Standard library.

iv

iv in std_logic_vector ( 8 * WORD_WIDTH - 1 downto 0 )

Port

Old values of the accumulators.

numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

WORD_WIDTH

WORD_WIDTH natural := 32

Generic

Word width of the circuit.