- i -

• ieee : Choose , counter , CS_adder , D_ff , Expander_stage , full_adder , full_adder_array , Initialisation_block , Initialisation_block.Reordered_UF2 , K_ROM , Last_transformation , Majority , RC_adder , reg , SHA2_Control_Unit , SHA2_core , Sigma_0 , Sigma_1 , T1 , T2 , test_SHA256_power_1A , test_SHA256_power_1B , test_SHA256_power_2A , test_SHA256_power_5A , Transf_round , Transf_round.Precomputed_UF1 , Transf_round.Reordered_UF1 , Transf_round.Reordered_UF2 , Transf_round_comb , tSHA256_core , tSHA256_core_multi , tSHA512_core , utils , w_sigma_0 , w_sigma_1
• init : SHA2_core.RTL
• input : Transf_round
• intermediate_sum2 : Transf_round.Precomputed_UF1
• intermediate_sum3 : Transf_round.Precomputed_UF1
• iv : Initialisation_block , Last_transformation , SHA2_core
• IV : test_SHA256_power_1A.Testbed , test_SHA256_power_1B.Testbed , test_SHA256_power_2A.Testbed , test_SHA256_power_5A.Testbed , tSHA256_core.Testbench , tSHA256_core_multi.Testbench , tSHA512_core.Testbench