RTL Architecture Reference

Architecture of the \(T_2\) step function block. More...

Signals
Sigma_0_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_0\) function block.
Maj_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Maj\) function block.

Instantiations
sigma	Sigma_0 <Entity Sigma_0>
	\(\Sigma_0\) function block
maj	Majority <Entity Majority>
	\(Maj\) function block

Detailed Description

Architecture of the \(T_2\) step function block.

Member Data Documentation

maj

maj Majority

Instantiation

\(Maj\) function block

Maj_o

Maj_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Maj\) function block.

sigma

sigma Sigma_0

Instantiation

\(\Sigma_0\) function block

Sigma_0_o

Sigma_0_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_0\) function block.