Transf_round_comb Entity Reference

Combinatorial part of the transformation round block. More...

Inheritance diagram for Transf_round_comb:

Entities
Naive	architecture
	Straightforward architecture of the combinatorial part of the transformation round block. More...
Unrolled	architecture
	Unrolled architecture of the combinatorial part of the transformation round More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Generics
WORD_WIDTH	natural := 32
	Width of the words of the Compressor.
UNROLLING_FACTOR	natural := 1
	Number of SHA-256 steps performed by a single round.

Ports
a_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(A\).
b_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(B\).
c_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(C\).
d_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(D\).
e_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(E\).
f_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(F\).
g_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(G\).
h_in	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input value of the accumulator \(H\).
K	in std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )
	Constant \(K\) words.
W	in std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )
	Expanded message words.
a_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(A\).
b_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(B\).
c_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(C\).
d_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(D\).
e_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(E\).
f_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(F\).
g_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(G\).
h_out	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output value of the accumulator \(H\).

Detailed Description

Combinatorial part of the transformation round block.

Member Data Documentation

a_in

a_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(A\).

a_out

a_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(A\).

b_in

b_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(B\).

b_out

b_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(B\).

c_in

c_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(C\).

c_out

c_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(C\).

d_in

d_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(D\).

d_out

d_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(D\).

e_in

e_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(E\).

e_out

e_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(E\).

f_in

f_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(F\).

f_out

f_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(F\).

g_in

g_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(G\).

g_out

g_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(G\).

h_in

h_in in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input value of the accumulator \(H\).

h_out

h_out out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output value of the accumulator \(H\).

ieee

ieee

Library

Standard library.

K

K in std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )

Port

Constant \(K\) words.

numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

UNROLLING_FACTOR

UNROLLING_FACTOR natural := 1

Generic

Number of SHA-256 steps performed by a single round.

W

W in std_logic_vector ( ( UNROLLING_FACTOR * WORD_WIDTH ) - 1 downto 0 )

Port

Expanded message words.

WORD_WIDTH

WORD_WIDTH natural := 32

Generic

Width of the words of the Compressor.