RTL Architecture Reference

Architecture of the Carry Save Adder. More...

Signals
t	std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )
	Partial sums vector.
c	std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )
	Carry vector.

Instantiations
carry_save_logic	full_adder_array <Entity full_adder_array>
	Full adder array to precompute the carry bits.
rca	RC_adder <Entity RC_adder>
	Final addition between the partial sum and the carry bits.

Detailed Description

Architecture of the Carry Save Adder.

The Carry-Save adder first computes, for each bit of the imputs, the sum of the three input bits, and their carry bit. Therefore, the carry vector is added to the partial sum vector

Member Data Documentation

c

c std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Carry vector.

carry_save_logic

carry_save_logic full_adder_array

Instantiation

Full adder array to precompute the carry bits.

rca

rca RC_adder

Instantiation

Final addition between the partial sum and the carry bits.

t

t std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Partial sums vector.