SHA-2 Workbench  1.0
RTL Architecture Reference

Architectuere of the full adder array. More...

Signals

c_temp  std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )
 Temporary array of carry outputs.

Instantiations

fa  full_adder <Entity full_adder>
 Each one of the full adder of the array.

Detailed Description

Architectuere of the full adder array.

Member Data Documentation

◆ c_temp

c_temp std_logic_vector ( width - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Temporary array of carry outputs.

◆ fa

fa full_adder
Instantiation

Each one of the full adder of the array.