RTL Architecture Reference

Architecture of the \(T_1\) step function block. More...

Signals
Sigma_1_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_1\) function block.
Ch_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Ch\) function block.

Instantiations
sigma	Sigma_1 <Entity Sigma_1>
	\(\Sigma_1\) function block
choose	Choose <Entity Choose>
	\(Ch\) function block

Detailed Description

Architecture of the \(T_1\) step function block.

Member Data Documentation

Ch_o

Ch_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Ch\) function block.

choose

choose Choose

Instantiation

\(Ch\) function block

sigma

sigma Sigma_1

Instantiation

\(\Sigma_1\) function block

Sigma_1_o

Sigma_1_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_1\) function block.