| 
    SHA-2 Workbench
    1.0
    
   | 
 
Full adder. More...
  
 Entities | |
| RTL | architecture | 
| Architecture of the full adder.  More... | |
Libraries | |
| ieee | |
| Standard library.   | |
Use Clauses | |
| std_logic_1164 | |
| Standard 9-values logic library.   | |
Ports | |
| x | in std_logic | 
| First input of the full adder.   | |
| y | in std_logic | 
| Second input of the full adder.   | |
| c_in | in std_logic | 
| Carry input of the full adder.   | |
| s | out std_logic | 
| Sum output of the full adder.   | |
| c_out | out std_logic | 
| Carry output of the full adder.   | |
Full adder.
      
  | 
  Port | 
Carry input of the full adder.
      
  | 
  Port | 
Carry output of the full adder.
      
  | 
  Library | 
Standard library.
      
  | 
  Port | 
Sum output of the full adder.
      
  | 
  Package | 
Standard 9-values logic library.
      
  | 
  Port | 
First input of the full adder.
      
  | 
  Port | 
Second input of the full adder.