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SHA-2 Workbench
1.0
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Full adder. More...
Entities | |
| RTL | architecture |
| Architecture of the full adder. More... | |
Libraries | |
| ieee | |
| Standard library. | |
Use Clauses | |
| std_logic_1164 | |
| Standard 9-values logic library. | |
Ports | |
| x | in std_logic |
| First input of the full adder. | |
| y | in std_logic |
| Second input of the full adder. | |
| c_in | in std_logic |
| Carry input of the full adder. | |
| s | out std_logic |
| Sum output of the full adder. | |
| c_out | out std_logic |
| Carry output of the full adder. | |
Full adder.
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Port |
Carry input of the full adder.
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Port |
Carry output of the full adder.
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Library |
Standard library.
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Port |
Sum output of the full adder.
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Package |
Standard 9-values logic library.
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Port |
First input of the full adder.
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Port |
Second input of the full adder.