T1 Entity Reference

\(T_1\) step function block More...

Inheritance diagram for T1:

Entities
RTL	architecture
	Architecture of the \(T_1\) step function block. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Generics
WORD_WIDTH	natural := 32

Ports
e	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input \(E\) to the step function block.
f	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input \(F\) to the step function block.
g	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input \(G\) to the step function block.
h	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Input \(H\) to the step function block.
K	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Constant \(K\) word input to the step function block.
W	in std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Expanded message word input to the step function block.
o	out std_logic_vector ( WORD_WIDTH - 1 downto 0 )
	Output of the step function block.

Detailed Description

\(T_1\) step function block

This component computes the function

\[ {T_1}_t = H_t + \Sigma_1\left(E_t\right) + Ch\left(E_t, F_t, G_t\right) + K_t + W_t \quad \forall t\in\left[0,R-1\right] \]

Member Data Documentation

e

e in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input \(E\) to the step function block.

f

f in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input \(F\) to the step function block.

g

g in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input \(G\) to the step function block.

h

h in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Input \(H\) to the step function block.

ieee

ieee

Library

Standard library.

K

K in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Constant \(K\) word input to the step function block.

numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

o

o out std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Output of the step function block.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

W

W in std_logic_vector ( WORD_WIDTH - 1 downto 0 )

Port

Expanded message word input to the step function block.

WORD_WIDTH

WORD_WIDTH natural := 32

Generic