reg Entity Reference

D register. More...

Inheritance diagram for reg:

Entities
RTL	architecture
	Architecture of the D register. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.

Generics
width	natural := 32
	Width of the register.

Ports
clk	in std_logic
	Clock of this component.
not_rst	in std_logic
	Active-low asynchronous reset signal.
en	in std_logic
	Enable signal.
d	in std_logic_vector ( width - 1 downto 0 )
	Input word of the register.
q	out std_logic_vector ( width - 1 downto 0 )
	Output word of the register.

Detailed Description

D register.

Member Data Documentation

clk

clk in std_logic

Port

Clock of this component.

d

d in std_logic_vector ( width - 1 downto 0 )

Port

Input word of the register.

en

en in std_logic

Port

Enable signal.

ieee

ieee

Library

Standard library.

not_rst

not_rst in std_logic

Port

Active-low asynchronous reset signal.

q

q out std_logic_vector ( width - 1 downto 0 )

Port

Output word of the register.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

width

width natural := 32

Generic

Width of the register.