Spatially-reordered, non-unrolled architecture of the transformation round block. More...

Libraries
ieee
	Standard library.
shacomps
	Basic SHA components library.
components
	Basic integrated circuits components library.

Use Clauses
numeric_std
	Arithmetic library, included for the unsigned modulo addition.

Signals
feedback	*std_logic_vector ( 8 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Internal output signal, to be used as feedback input.
mux_output	*std_logic_vector ( 8 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Output of the multiplexer, and input of the precomputation stage.
reg_input	*std_logic_vector ( 10 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Input of the compressor pipeline register.
reg_output	*std_logic_vector ( 10 WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )**
	Output of the compressor pipeline register.
sigma_0	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_0\) functional block.
maj_output	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Majority\) functional block.
sigma_1	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(\Sigma_1\) functional block.
ch_output	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(Choose\) functional block.
t1	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Value of the \(T_1\) step function, computed during the final computation phase.

Instantiations
sigma0	Sigma_0 <Entity Sigma_0>
	\(\Sigma_0\) component
maj	Majority <Entity Majority>
	\(\Majority\) component
sigma1	Sigma_1 <Entity Sigma_1>
	\(\Sigma_1\) component
ch	Choose <Entity Choose>
	\(\Choose\) component
pipeline_reg	reg <Entity reg>
	Pipeline register of the compressor pipeline.

Aliases
a_mux_out	is mux_output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) input for the stage.
b_mux_out	is mux_output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) input for the stage.
c_mux_out	is mux_output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) input for the stage.
d_mux_out	is mux_output** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the accumulator \(D\) input for the stage.
e_mux_out	is mux_output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) input for the stage.
f_mux_out	is mux_output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) input for the stage.
g_mux_out	is mux_output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) input for the stage.
h_mux_out	is mux_output ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) input for the stage.
a_reg_in	is reg_input** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Precomputed value of the accumulator \(A\) input to the pipeline register.
p1_reg_in	is reg_input** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Precomputed value of the parameter \(P^*_1\) input to the pipeline register.
b_reg_in	is reg_input** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Precomputed value of the accumulator \(B\) input to the pipeline register.
c_reg_in	is reg_input** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Precomputed value of the accumulator \(C\) input to the pipeline register.
d_reg_in	is reg_input** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Precomputed value of the accumulator \(D\) input to the pipeline register.
p2_reg_in	is reg_input** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Precomputed value of the parameter \(P^*_2\) input to the pipeline register.
e_reg_in	is reg_input** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Precomputed value of the accumulator \(E\) input to the pipeline register.
f_reg_in	is reg_input** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Precomputed value of the accumulator \(F\) input to the pipeline register.
g_reg_in	is reg_input** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Precomputed value of the accumulator \(G\) input to the pipeline register.
h_reg_in	is reg_input ( WORD_WIDTH - 1 downto 0 )
	Precomputed value of the parameter \(H^*\) input to the pipeline register.
valid_reg	is reg_output** ( 10 * WORD_WIDTH )**
	Flag of validity for the register.
a_reg_out	is reg_output** ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )**
	Value of the accumulator \(A\) input to the final calculation phase.
p1_reg_out	is reg_output** ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )**
	Value of the parameter \(P^*_1\) input to the final calculation phase.
b_reg_out	is reg_output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(B\) input to the final calculation phase.
c_reg_out	is reg_output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(C\) input to the final calculation phase.
d_reg_out	is reg_output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(D\) input to the final calculation phase.
p2_reg_out	is reg_output** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the parameter \(P^*_2\) input to the final calculation phase.
e_reg_out	is reg_output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) input to the final calculation phase.
f_reg_out	is reg_output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) input to the final calculation phase.
g_reg_out	is reg_output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) input to the final calculation phase.
h_reg_out	is reg_output ( WORD_WIDTH - 1 downto 0 )
	Value of the parameter \(H^*\) input to the final calculation phase.
a_feedback	is feedback** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) output from the compressor round.
b_feedback	is feedback** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) output from the compressor round.
c_feedback	is feedback** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) output from the compressor round.
d_feedback	is feedback** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the accumulator \(D\) output from the compressor round.
e_feedback	is feedback** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) output from the compressor round.
f_feedback	is feedback** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) output from the compressor round.
g_feedback	is feedback** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) output from the compressor round.
h_feedback	is feedback ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the compressor round.
valid_out	is output** ( 8 * WORD_WIDTH )**
	Flag of validity for the output register.
a_out	is output** ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )**
	Value of the accumulator \(A\) output from the stage.
b_out	is output** ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )**
	Value of the accumulator \(B\) output from the stage.
c_out	is output** ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )**
	Value of the accumulator \(C\) output from the stage.
d_out	is output** ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )**
	Value of the accumulator \(D\) output from the stage.
e_out	is output** ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )**
	Value of the accumulator \(E\) output from the stage.
f_out	is output** ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )**
	Value of the accumulator \(F\) output from the stage.
g_out	is output** ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )**
	Value of the accumulator \(G\) output from the stage.
h_out	is output ( WORD_WIDTH - 1 downto 0 )
	Value of the accumulator \(H\) output from the stage.

Detailed Description

Spatially-reordered, non-unrolled architecture of the transformation round block.

Implementation of the architecture originally proposed in H. Michail, A. Milidonis, A. Kakarountas, and C. Goutis, "Novel high throughput implementation of SHA-256 hash function through pre-computation technique", in ICECS 2005 - 12th IEEE International Conference on Electronics, Circuits, and Systems, 2005.

Member Data Documentation

◆ a_feedback

a_feedback is feedback ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ a_mux_out

a_mux_out is mux_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) input for the stage.

◆ a_out

a_out is output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) output from the stage.

◆ a_reg_in

a_reg_in is reg_input ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(A\) input to the pipeline register.

◆ a_reg_out

a_reg_out is reg_output ( 10 * WORD_WIDTH - 1 downto 9 * WORD_WIDTH )

Alias

Value of the accumulator \(A\) input to the final calculation phase.

◆ b_feedback

b_feedback is feedback ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ b_mux_out

b_mux_out is mux_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) input for the stage.

◆ b_out

b_out is output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) output from the stage.

◆ b_reg_in

b_reg_in is reg_input ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(B\) input to the pipeline register.

◆ b_reg_out

b_reg_out is reg_output ( 8 * WORD_WIDTH - 1 downto 7 * WORD_WIDTH )

Alias

Value of the accumulator \(B\) input to the final calculation phase.

◆ c_feedback

c_feedback is feedback ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ c_mux_out

c_mux_out is mux_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) input for the stage.

◆ c_out

c_out is output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) output from the stage.

◆ c_reg_in

c_reg_in is reg_input ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(C\) input to the pipeline register.

◆ c_reg_out

c_reg_out is reg_output ( 7 * WORD_WIDTH - 1 downto 6 * WORD_WIDTH )

Alias

Value of the accumulator \(C\) input to the final calculation phase.

◆ ch

ch Choose

Instantiation

\(\Choose\) component

◆ ch_output

ch_output std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Choose\) functional block.

◆ components

components

Library

Basic integrated circuits components library.

◆ d_feedback

d_feedback is feedback ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ d_mux_out

d_mux_out is mux_output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) input for the stage.

◆ d_out

d_out is output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) output from the stage.

◆ d_reg_in

d_reg_in is reg_input ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(D\) input to the pipeline register.

◆ d_reg_out

d_reg_out is reg_output ( 6 * WORD_WIDTH - 1 downto 5 * WORD_WIDTH )

Alias

Value of the accumulator \(D\) input to the final calculation phase.

◆ e_feedback

e_feedback is feedback ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ e_mux_out

e_mux_out is mux_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) input for the stage.

◆ e_out

e_out is output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) output from the stage.

◆ e_reg_in

e_reg_in is reg_input ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(E\) input to the pipeline register.

◆ e_reg_out

e_reg_out is reg_output ( 4 * WORD_WIDTH - 1 downto 3 * WORD_WIDTH )

Alias

Value of the accumulator \(E\) input to the final calculation phase.

◆ f_feedback

f_feedback is feedback ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ f_mux_out

f_mux_out is mux_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) input for the stage.

◆ f_out

f_out is output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) output from the stage.

◆ f_reg_in

f_reg_in is reg_input ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Precomputed value of the accumulator \(F\) input to the pipeline register.

◆ f_reg_out

f_reg_out is reg_output ( 3 * WORD_WIDTH - 1 downto 2 * WORD_WIDTH )

Alias

Value of the accumulator \(F\) input to the final calculation phase.

◆ feedback

feedback std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Internal output signal, to be used as feedback input.

◆ g_feedback

g_feedback is feedback ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ g_mux_out

g_mux_out is mux_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) input for the stage.

◆ g_out

g_out is output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) output from the stage.

◆ g_reg_in

g_reg_in is reg_input ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Precomputed value of the accumulator \(G\) input to the pipeline register.

◆ g_reg_out

g_reg_out is reg_output ( 2 * WORD_WIDTH - 1 downto WORD_WIDTH )

Alias

Value of the accumulator \(G\) input to the final calculation phase.

◆ h_feedback

h_feedback is feedback ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the compressor round.

This temporary signal is employed to perform the feedback

◆ h_mux_out

h_mux_out is mux_output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) input for the stage.

◆ h_out

h_out is output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the accumulator \(H\) output from the stage.

◆ h_reg_in

h_reg_in is reg_input ( WORD_WIDTH - 1 downto 0 )

Alias

Precomputed value of the parameter \(H^*\) input to the pipeline register.

◆ h_reg_out

h_reg_out is reg_output ( WORD_WIDTH - 1 downto 0 )

Alias

Value of the parameter \(H^*\) input to the final calculation phase.

◆ ieee

ieee

Library

Standard library.

◆ maj

maj Majority

Instantiation

\(\Majority\) component

◆ maj_output

maj_output std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(Majority\) functional block.

◆ mux_output

mux_output std_logic_vector ( 8 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the multiplexer, and input of the precomputation stage.

◆ numeric_std

numeric_std

Package

Arithmetic library, included for the unsigned modulo addition.

◆ p1_reg_in

p1_reg_in is reg_input ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(P^*_1\) input to the pipeline register.

◆ p1_reg_out

p1_reg_out is reg_output ( 9 * WORD_WIDTH - 1 downto 8 * WORD_WIDTH )

Alias

Value of the parameter \(P^*_1\) input to the final calculation phase.

◆ p2_reg_in

p2_reg_in is reg_input ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Precomputed value of the parameter \(P^*_2\) input to the pipeline register.

◆ p2_reg_out

p2_reg_out is reg_output ( 5 * WORD_WIDTH - 1 downto 4 * WORD_WIDTH )

Alias

Value of the parameter \(P^*_2\) input to the final calculation phase.

◆ pipeline_reg

pipeline_reg reg

Instantiation

Pipeline register of the compressor pipeline.

It works also as working register

◆ reg_input

reg_input std_logic_vector ( 10 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Input of the compressor pipeline register.

◆ reg_output

reg_output std_logic_vector ( 10 * WORD_WIDTH downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the compressor pipeline register.

◆ shacomps

shacomps

Library

Basic SHA components library.

◆ sigma0

sigma0 Sigma_0

Instantiation

\(\Sigma_0\) component

◆ sigma1

sigma1 Sigma_1

Instantiation

\(\Sigma_1\) component

◆ sigma_0

sigma_0 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_0\) functional block.

◆ sigma_1

sigma_1 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(\Sigma_1\) functional block.

◆ t1

t1 std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Value of the \(T_1\) step function, computed during the final computation phase.

◆ valid_out

valid_out is output ( 8 * WORD_WIDTH )

Alias

Flag of validity for the output register.

◆ valid_reg

valid_reg is reg_output ( 10 * WORD_WIDTH )

Alias

Flag of validity for the register.

Libraries

Use Clauses

Signals

Instantiations

Aliases

Detailed Description

Member Data Documentation

◆ a_feedback

◆ a_mux_out

◆ a_out

◆ a_reg_in

◆ a_reg_out

◆ b_feedback

◆ b_mux_out

◆ b_out

◆ b_reg_in

◆ b_reg_out

◆ c_feedback

◆ c_mux_out

◆ c_out

◆ c_reg_in

◆ c_reg_out

◆ ch

◆ ch_output

◆ components

◆ d_feedback

◆ d_mux_out

◆ d_out

◆ d_reg_in

◆ d_reg_out

◆ e_feedback

◆ e_mux_out

◆ e_out

◆ e_reg_in

◆ e_reg_out

◆ f_feedback

◆ f_mux_out

◆ f_out

◆ f_reg_in

◆ f_reg_out

◆ feedback

◆ g_feedback

◆ g_mux_out

◆ g_out

◆ g_reg_in

◆ g_reg_out

◆ h_feedback

◆ h_mux_out

◆ h_out

◆ h_reg_in

◆ h_reg_out

◆ ieee

◆ maj

◆ maj_output

◆ mux_output

◆ numeric_std

◆ p1_reg_in

◆ p1_reg_out

◆ p2_reg_in

◆ p2_reg_out

◆ pipeline_reg

◆ reg_input

◆ reg_output

◆ shacomps

◆ sigma0

◆ sigma1

◆ sigma_0

◆ sigma_1

◆ t1

◆ valid_out

◆ valid_reg