CS_adder Entity Reference

Carry-Save adder. More...

Inheritance diagram for CS_adder:

Entities
RTL	architecture
	Architecture of the Carry Save Adder. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.

Generics
width	integer := 8
	Width of the adder.

Ports
x	in std_logic_vector ( width - 1 downto 0 )
	First input operand of the adder.
y	in std_logic_vector ( width - 1 downto 0 )
	Second input operand of the adder.
z	in std_logic_vector ( width - 1 downto 0 )
	Third input operand of the adder.
c_in	in std_logic
	Carry input of the adder.
s	out std_logic_vector ( width - 1 downto 0 )
	Sum output of the adder.
c_out	out std_logic
	Carry output of the adder.

Detailed Description

Carry-Save adder.

Three-operands adder with delay comparable to a two-operands adder

Member Data Documentation

c_in

c_in in std_logic

Port

Carry input of the adder.

c_out

c_out out std_logic

Port

Carry output of the adder.

ieee

ieee

Library

Standard library.

s

s out std_logic_vector ( width - 1 downto 0 )

Port

Sum output of the adder.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

width

width integer := 8

Generic

Width of the adder.

x

x in std_logic_vector ( width - 1 downto 0 )

Port

First input operand of the adder.

y

y in std_logic_vector ( width - 1 downto 0 )

Port

Second input operand of the adder.

z

z in std_logic_vector ( width - 1 downto 0 )

Port

Third input operand of the adder.