Majority Entity Reference

\(Maj\) function block More...

Inheritance diagram for Majority:

Entities
RTL	architecture
	Architecture of the \(Maj\) function block. More...

Libraries
ieee
	Standard library.

Use Clauses
std_logic_1164
	Standard 9-values logic library.

Generics
width	natural := 32
	Width of the words of the Compressor.

Ports
x	in std_logic_vector ( width - 1 downto 0 )
	\(x\) input of the function block
y	in std_logic_vector ( width - 1 downto 0 )
	\(y\) input of the function block
z	in std_logic_vector ( width - 1 downto 0 )
	\(z\) input of the function block
o	out std_logic_vector ( width - 1 downto 0 )
	Output of the function block.

Detailed Description

\(Maj\) function block

This component computes the function

\[ Maj\left(x,y,z\right) = \left(x \wedge y\right) \oplus \left(x \wedge z\right) \oplus \left(y \wedge z\right) \]

Member Data Documentation

ieee

ieee

Library

Standard library.

o

o out std_logic_vector ( width - 1 downto 0 )

Port

Output of the function block.

std_logic_1164

std_logic_1164

Package

Standard 9-values logic library.

width

width natural := 32

Generic

Width of the words of the Compressor.

x

x in std_logic_vector ( width - 1 downto 0 )

Port

\(x\) input of the function block

y

y in std_logic_vector ( width - 1 downto 0 )

Port

\(y\) input of the function block

z

z in std_logic_vector ( width - 1 downto 0 )

Port

\(z\) input of the function block