Straightforward architecture of the combinatorial part of the transformation round block. More...

Signals
t1_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(T_1\) step function.
t2_o	std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
	Output of the \(T_2\) step function.

Instantiations
t1	T1 <Entity T1>
	\(T1\) step function
t2	T2 <Entity T2>
	\(T2\) step function

Detailed Description

Straightforward architecture of the combinatorial part of the transformation round block.

Direct implementation of the compression function of SHA-2:

\begin{aligned} A_{t+1} & = {T_1}_t + {T_2}_t & \quad \forall t\in\left[0,R-1\right] \\ B_{t+1} & = A_t & \quad \forall t\in\left[0,R-1\right] \\ C_{t+1} & = B_t & \quad \forall t\in\left[0,R-1\right] \\ D_{t+1} & = C_t & \quad \forall t\in\left[0,R-1\right] \\ E_{t+1} & = D_t + {T_1}_t & \quad \forall t\in\left[0,R-1\right] \\ F_{t+1} & = E_t & \quad \forall t\in\left[0,R-1\right] \\ G_{t+1} & = F_t & \quad \forall t\in\left[0,R-1\right] \\ H_{t+1} & = G_t & \quad \forall t\in\left[0,R-1\right] \end{aligned}

Member Data Documentation

◆ t1

t1 T1

Instantiation

\(T1\) step function

◆ t1_o

t1_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Output of the \(T_1\) step function.

◆ t2

t2 T2

Instantiation

\(T2\) step function

◆ t2_o

t2_o std_logic_vector ( WORD_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )